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a ad9244 14-bit, 40/65 msps a/d converter rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. features 14-bit, 40/65 msps adc low power: 550 mw at 65 msps 300 mw at 40 msps on-chip reference and sample-and-hold 750 mhz analog input bandwidth snr > 73 dbc to nyquist @ 65 msps sfdr > 86 dbc to nyquist @ 65 msps differential nonlinearity error = 0.7 lsb guaranteed no missing codes over full temperature range 1 v to 2 v p-p differential full-scale analog input range single 5 v analog supply, 3.3 v/5 v driver supply out-of-range indicator straight binary or twos complement output data clock duty cycle stabilizer output enable function 48-lead lqfp package applications communications subsystems (microcell, picocell) medical and high end imaging equipment ultrasound equipment general description the ad9244 is a monolithic, single 5 v supply, 14-bit, 40 msps/65 msps analog-to-digital converter with an on-chip, high performance sample-and-hold amplifier and voltage reference. the ad9244 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy at 40 msps/65 msps data rates and guarantees no missing codes over the full operating temperature range. the ad9244 has an on-board, programmable voltage reference. an external reference can also be used to suit the dc accuracy and temperature drift requirements of the application. a differential or single-ended clock input is used to control all internal conversion cycles. the digital output data can be pre- sented in straight binary or in twos complement format. an out-of-range (otr) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. fabricated on an advanced cmos process, the ad9244 is available in a 48-lead low profile quad flatpack package (lqfp) and is specified for operation over the industrial temperature range ( C 40 c to +85 c). product highlights low power the ad9244, at 550 mw, consumes a frac- tion of the power of presently available adcs in existing high speed solutions. if sampling the ad9244 delivers outstanding perfor- mance at input frequencies beyond the first nyquist zone. sampling at 65 msps with an input frequency of 100 mhz, the ad9244 delivers 71 db snr and 86 db sfdr. pin compatibility the ad9244 offers a seamless migration from the 12-bit, 65 msps ad9226. on-board sample-and-hold (sha) the versatile sha input can be configured for either single-ended or differ- ential inputs. out-of-range (otr) the otr output bit indicates when the input signal is beyond the ad9244 s input range. single supply the ad9244 uses a single 5 v power supply, simplifying system power supply design. it also features a separate digital output driver supply to accom- modate 3.3 v and 5 v logic families. functional block diagram clk vin+ vin dcs a gnd dgnd vref sense oeb d13?0 otr dfs av d d drvdd 14 14 ad9244 sha timing reference output register ref gnd reft refb vr cml clk+ ten stage pipeline adc
rev. a ? ad9244?pecifications dc specifications test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit resolution full vi 14 14 bits dc accuracy no missing codes full vi guaranteed guaranteed bits offset error full vi 0.3 1.4 0.3 1.4 % fsr gain error 1 full vi 0.6 2.0 0.6 2.0 % fsr differential nonlinearity (dnl) 2 full vi 1.0 1.0 lsb 25 cv 0.7 0.6 lsb integral nonlinearity (inl) 2 full v 1.4 1.3 lsb temperature drift offset error full v 2.0 2.0 ppm/ c gain error (ext vref) 1 full v 2.3 2.3 ppm/ c gain error (int vref) 3 full v 25 25 ppm/ c internal voltage reference output voltage error (2 vref) full vi 29 29 mv load regulation @ 1 ma full v 0.5 0.5 mv output voltage error (1 vref) full iv 15 15 mv load regulation @ 0.5 ma full v 0.25 0.25 mv input resistance full v 5 5 k ? input referred noise vref = 2 v 25 cv 0.8 0.8 lsb rms vref = 1 v 25 cv 1.5 1.5 lsb rms analog input input voltage range (differential) vref = 2 v full v 2 2 v p-p vref = 1 v full v 1 1 v p-p common-mode voltage full v 0.5 4 0.5 4 v input capacitance 4 25 cv 10 10 pf input bias current 5 25 cv 500 500 a analog bandwidth (full power) 25 cv 750 750 mhz power supplies supply voltages avdd full iv 4.75 5 5.25 4.75 5 5.25 v drvdd full iv 2.7 5.25 2.7 5.25 v supply current iavdd full v 109 64 ma idrvdd full v 12 8 ma psrr full v 0.05 0.05 % fsr power consumption dc input 6 full v 550 300 mw sine wave input full vi 590 640 345 370 mw notes 1 gain error is based on the adc only (with a fixed 2.0 v external reference). 2 measured at maximum clock rate, f in = 2.4 mhz, full-scale sine wave, with approximately 5 pf loading on each output bit. 3 includes internal voltage reference error. 4 input capacitance refers to the effective capacitance between one differential input pin and agnd. refer to figure 2d for the e quivalent analog input structure. 5 input bias current is due to the inputs looking like a resistor that is dependent on the clock rate. 6 measured with dc input at maximum clock rate. specifications subject to change without notice. (avdd = 5 v, drvdd = 3 v, f sample = 65 msps (?5) or 40 msps (?0), differential clock inputs, vref = 2 v, external reference, differential analog inputs, unless otherwise noted.)
rev. a ad9244 ? test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit snr f in = 2.4 mhz full vi 72.4 73.4 dbc 25 ci 74 .8 75.3 dbc f in = 15.5 mhz ( C 1 dbfs) full iv 72.0 dbc 25 cv 73 .7 dbc f in = 20 mhz full vi 72.1 dbc 25 ci 74 .7 dbc f in = 32.5 mhz full iv 70.8 dbc 25 ci 73 .0 dbc f in = 70 mhz full iv 69.9 dbc 25 cv 72 .2 dbc f in = 100 mhz 25 cv 71 .2 72.8 dbc f in = 200 mhz 25 cv 67 .2 68.3 dbc sinad f in = 2.4 mhz full vi 72.2 73.2 dbc 25 ci 74 .7 75.1 dbc f in = 20 mhz full vi 72 dbc 25 ci 74 .4 dbc f in = 32.5 mhz full iv 70.6 dbc 25 ci 72 .6 dbc f in = 70 mhz full iv 69.7 dbc 25 cv 71 .9 dbc f in = 100 mhz 25 cv 71 72 .4 dbc f in = 200 mhz 25 cv 59 .8 56.3 dbc enob f in = 2.4 mhz full vi 11.7 11.9 bits 25 ci 12.1 12.2 bits f in = 20 mhz full vi 11.7 bits 25 ci 12.1 bits f in = 32.5 mhz full iv 11.4 bits 25 ci 11.8 bits f in = 70 mhz full iv 11.3 bits 25 cv 11.7 bits f in = 100 mhz 25 cv 11.5 11.7 bits f in = 200 mhz 25 cv 9.6 9.1 bits thd f in = 2.4 mhz full vi C 78.4 C 80.7 dbc 25 ci C 90.0 C 89.7 dbc f in = 20 mhz full vi C 80.4 dbc 25 ci C 89.4 dbc f in = 32.5 mhz full iv C 79.2 dbc 25 ci C 84.6 dbc f in = 70 mhz full iv C 78.7 dbc 25 cv C 84.1 dbc f in = 100 mhz 25 cv C 83.0 C 83.2 dbc f in = 200 mhz 25 cv C 60.7 C 56.6 dbc worst 2 or 3 f in = 2.4 mhz 25 cv C 94.5 C 93.7 dbc f in = 20 mhz 25 cv C 92.8 dbc f in = 32.5 mhz 25 cv C 86.5 dbc f in = 70 mhz 25 cv C 86.1 dbc f in = 100 mhz 25 cv C 86.2 C 84.5 dbc f in = 200 mhz 25 cv C 60.7 C 56.6 dbc ac specifications (avdd = 5 v, drvdd = 3 v, f sample = 65 msps (?5) or 40 msps (?0), differential clock inputs, vref = 2 v, external reference, a in = ?.5 dbfs, differential analog inputs, unless otherwise noted.)
rev. a ? ad9244 digital specifications (avdd = 5 v, drvdd = 3 v, vref = 2 v, external reference, unless otherwise noted.) test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit digital inputs logic 1 voltage (oeb, drvdd = 3 v) full iv 2 2 v logic 1 voltage (oeb, drvdd = 5 v) full iv 3.5 3.5 v logic 0 voltage (oeb) full iv 0.8 0.8 v logic 1 voltage (dfs, dcs) full iv 3.5 3.5 v logic 0 voltage (dfs, dcs) full iv 0.8 0.8 v input current full iv 10 10 a input capacitance full v 5 5 pf clock input parameters differential input voltage full iv 0.4 0.4 v p-p clk?oltage 1 full iv 0.25 0.25 v internal clock common-mode full v 1.6 1.6 v single-ended input voltage logic 1 voltage full iv 2 2 v logic 0 voltage full iv 0.8 0.8 v input capacitance full v 5 5 pf input resistance full v 100 100 k ? digital outputs (drvdd = 5 v) 2 logic 1 voltage (i oh = 50 a) full iv 4.5 4.5 v logic 0 voltage (i ol = 50 a) full iv 0.1 0.1 v logic 1 voltage (i oh = 0.5 ma) full iv 2.4 2.4 v logic 0 voltage (i ol = 1.6 ma) full iv 0.4 0.4 v digital outputs (drvdd = 3 v) 2 logic 1 voltage (i oh = 50 a) full iv 2.95 2.95 v logic 0 voltage (i ol = 50 a) full iv 0.05 0.05 v logic 1 voltage (i oh = 0.5 ma) full iv 2.8 2.8 v logic 0 voltage (i ol = 1.6 ma) full iv 0.4 0.4 v notes 1 see clock section of theory of operation for more details. 2 output voltage levels measured with 5 pf load on each output. specifications subject to change without notice. test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit sfdr f in = 2.4 mhz full vi 78.6 82.5 dbc 25 ci 9 4.5 93.7 dbc f in = 15.5 mhz (? dbfs) full iv 83 dbc 25 cv 90 dbc f in = 20 mhz full iv 81.4 dbc 25 ci 9 1.8 dbc f in = 32.5 mhz full iv 80.0 dbc 25 ci 8 6.4 dbc f in = 70 mhz full iv 79.5 dbc 25 cv 8 6.1 dbc f in = 100 mhz 25 cv 8 6.2 84.5 dbc f in = 200 mhz 25 cv 6 0.7 56.6 dbc ac specifications (continued)
rev. a ad9244 ? test ad9244bst-65 ad9244bst-40 parameter temp level min typ max min typ max unit clock input parameters maximum conversion rate full vi 65 40 mhz minimum conversion rate full v 500 500 khz clock period 1 full v 15.4 25 ns clock pulsewidth high 2 full v 4 4 ns clock pulsewidth low 2 full v 4 4 ns clock pulsewidth high 3 full v 6.9 11.3 ns clock pulsewidth low 3 full v 6.9 11.3 ns data output parameters output delay (t pd ) 4 full v 3.5 7 3.5 7 ns pipeline delay (latency) full v 8 8 clock cycles aperture delay (t a ) full v 1.5 1.5 ns aperture uncertainty (jitter) full v 0.3 0.3 ps rms output enable delay full v 15 15 ns out-of-range recovery time full v 2 1 clock cycles notes 1 the clock period may be extended to 2 s with no degradation in specified performance at 25 c. 2 with duty cycle stabilizer enabled. 3 with duty cycle stabilizer disabled. 4 measured from clock 50% transition to data 50% transition with 5 pf load on each output. specifications subject to change without notice (avdd = 5 v, drvdd = 3 v, unless otherwise noted.) switching specifications n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 analog input clock data out t pd t a n? n? n? n? n? n? n? n? n? n n+1 figure 1. input timing
rev. a ? ad9244 absolute maximum ratings 1 with mnemonic respect to min max unit electrical avdd agnd C 0.3 +6.5 v drvdd dgnd C 0.3 +6.5 v agnd dgnd C 0.3 +0.3 v avdd drvdd C 6.5 +6.5 v refgnd agnd C 0.3 +0.3 v clk+, clk C , dcs agnd C 0.3 avdd + 0.3 v dfs agnd C 0.3 avdd + 0.3 v vin+, vin C agnd C 0.3 avdd + 0.3 v vref agnd C 0.3 avdd + 0.3 v sense agnd C 0.3 avdd + 0.3 v refb, reft agnd C 0.3 avdd + 0.3 v cml agnd C 0.3 avdd + 0.3 v vr agnd C 0.3 avdd + 0.3 v otr dgnd C 0.3 drvdd + 0.3 v d0 C d13 dgnd C 0.3 drvdd + 0.3 v oeb dgnd C 0.3 drvdd + 0.3 v environmental 2 junction temperature 150 c storage temperature C 65 +150 c operating temperature C 40 +85 c lead temperature (10 sec) 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. 2 typical thermal impedances; ja = 50.0 c/w; jc = 17.0 c/w. these measure- ments were taken on a 4-layer board in still air, in accordance with eia/jesd51-7. explanation of test levels test level i. 100% production tested. ii. 100% production tested at 25 c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25 c; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. ordering guide model temperature range package description package option ad9244bst-65 C 40 c to +85 c 48-lead low profile quad flatpack package st-48 ad9244bst-40 C 40 c to +85 c 48-lead low profile quad flatpack package st-48 ad9244bstrl-65 C 40 c to +85 c 48-lead low profile quad flatpack package st-48 ad9244bstrl-40 C 40 c to +85 c 48-lead low profile quad flatpack package st-48 AD9244-65PCB evaluation board ad9244-40pcb evaluation board caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9244 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. a ad9244 ? pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a gnd a gnd av d d av d d a gnd clk clk+ nic oeb d0 (lsb) d1 d2 d3 dgnd drvdd d4 d5 d6 d7 d8 d9 dgnd drvdd d10 d11 d12 d13 (msb) otr drvdd dgnd av d d a gnd a gnd av d d dfs sense vr vin vin+ cml nic dcs reft reft refb refb refgnd vref ad9244 top view ( not to scale) pin function descriptions pin no. mnemonic description 1, 2, 5, 32, 33 agnd analog ground. 3, 4, 31, 34 avdd analog supply voltage. 6, 7 clk C , clk+ differential clock inputs. 8, 44 nic no internal connection. 9 oeb digital output enable (active low). 10 d0 (lsb) least significant bit, digital output. 11 C 13, 16 C 21, d1 C d3, d4 C d9, digital outputs. 24 C 26 d10 C d12 14, 22, 30 dgnd digital ground. 15, 23, 29 drvdd digital supply voltage. 27 d13 (msb) most significant bit, digital output. 28 otr out-of-range indicator (logic 1 indicates otr). 35 dfs data format select. connect to agnd for straight binary, avdd for twos complement. 36 sense internal reference control. 37 vref internal reference. 38 refgnd reference ground. 39 C 42 refb, reft internal reference decoupling. 43 dcs 50% duty cycle stabilizer. connect to avdd to activate 50% duty cycle stabilizer, agnd for external control of both clock edges. 45 cml common-mode reference (0.5 avdd). 46, 47 vin+, vin C differential analog inputs. 48 vr internal bias decoupling.
rev. a ? ad9244 terminology analog bandwidth (full power bandwidth) the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential analog input voltage range the peak-to-peak differential voltage must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. peak-to-peak differential is computed by rotating the input phase 180 and taking the peak measurement again. then the difference is found between the two peak measurements. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes must be present over all operating ranges. dual tone sfdr * the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. effective number of bits (enob) the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its mea- sured sinad using the following formula: n sinad = () C ./. 176 602 gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last code transition should occur at an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. common-mode rejection ratio (cmrr) common-mode (cm) signals appearing on vin+ and vin C are ideally rejected by the differential front end of the adc. with a full-scale cm signal driving both vin+ and vin C , cmrr is the ratio of the amplitude of the full-scale input cm signal to the amplitude of signal that is not rejected , expressed in dbfs. if sampling due to the effects of aliasing, an adc is not necessarily limited to nyquist sampling. higher sampled frequencies will be aliased down into the first nyquist zone (dc C f clock /2) on the output of the adc. care must be taken that the bandwidth of the sampled signal does not overlap nyquist zones and alias onto itself. nyquist sampling performance is limited by the band- width of the input sha and clock jitter (noise caused by jitter increases as the input frequency increases). integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. minimum conversion rate the clock rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the clock rate at which parametric testing is performed. nyquist sampling when the frequency components of the analog input are below the nyquist frequency (f clock /2), this is often referred to as nyquist sampling. out-of-range recovery time the time it takes for the adc to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. power supply rejection ratio the change in full scale from the value with the supply at its minimum limit to the value with the supply at its maximum limit. signal-to-noise-and-distortion (sinad) * the ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below the nyquist fre- quency, including harmonics but excluding dc. signal-to-noise ratio (snr) * the ratio of the rms signal amplitude to the rms value of the sum of all other spectral compo nents below the nyquist fre- quency, excluding the first six harmonics and dc. spurious-free dynamic range (sfdr) * the difference in db between the rms amplitude of the input signal and the peak spurious signal. temperature drift the temperature drift for offset error and gain error specifies the maximum change from the initial (25 c) value to the value at t min or t max . total harmonic distortion (thd) * the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. offset error the major carry transition should occur for an analog value 1/2 lsb below vin+ = vin C . offset error is defined as the de viation of the actual transition from that point. * ac specifications may be reported in dbc (degrades as signal levels are lowered) or in dbfs (always related back to converter full scale).
rev. a ad9244 ? agnd avdd d. vin+, vin figure 2. equivalent circuits drvdd dgnd drvdd a. d0?13, otr d gnd drvdd 200 b. three-state (oeb) 200 agnd avdd clk buffer c. clk+, clk avdd agnd 200 e. dfs, dcs, sense agnd avdd f. vref, reft, refb, vr, cml
rev. a ?0 ad9244?ypical performance characteristics frequency ?mhz 0 ?20 amplitude ?dbfs ?0 ?0 ?0 ?0 ?00 0510 15 20 25 30 snr = 74.8dbc sfdr = 93.6dbc 32.5 tpc 1. single-tone fft, f in = 5 mhz frequency ?mhz 0 ?20 amplitude ?dbfs ?0 ?0 ?0 ?0 ?00 0510 15 20 25 30 snr = 74.0dbc sfdr = 87.0dbc 32.5 tpc 2. single-tone fft, f in = 31 mhz frequency ?mhz 0 ?20 amplitude ?dbfs ?0 ?0 ?0 ?0 ?00 0510 15 20 25 30 snr = 68.0dbc sfdr = 59.5dbc 30.72 tpc 3. single-tone fft, f in = 190 mhz, f sample = 61.44 msps (avdd = 5.0 v, drvdd = 3.0 v, f sample = 65 msps with clk duty cycle stabilizer enabled, t a = 25 c, differential analog input, common-mode voltage (vcm) = 2.5 v, input amplitude (a in ) = ?.5 dbfs, vref = 2.0 v external, fft length = 8 k, unless otherwise noted.) a in ?dbfs 100 40 dbfs and dbc 90 80 70 60 50 ?0 ?5 ?0 ?5 ?0 ? 0 sfdr ?dbfs sfdr ?dbc snr ?dbfs snr ?dbc sfdr = 90dbc reference line tpc 4. single-tone snr/sfdr vs. a in , f in = 5 mhz a in ?dbfs 40 ?0 0 ?5 dbfs and dbc ?0 ?5 ?0 ? 100 90 80 60 50 70 sfdr ?dbfs snr ?dbfs sfdr ?dbc snr ?dbc sfdr = 90dbc reference line tpc 5. single-tone snr/sfdr vs a in , f in = 31 mhz a in ?dbfs 40 0 ?5 dbfs and dbc ?0 ?5 ?0 ? 100 90 80 60 50 70 snr ?dbfs sfdr ?dbc snr ?dbc ?0 sfdr ?dbfs sfdr = 90dbc reference line tpc 6. single-tone snr/sfdr vs. a in , f in = 190 mhz, f sample = 61.44 msps
rev. a ad9244 ?1 input frequency ?mhz sinad ?dbc 75 65 67 20 140 40 60 80 100 120 0 2v span 1v span enob ?bits 12.2 10.5 11.8 69 71 73 11.5 11.2 10.8 tpc 7. sinad/enob vs. input frequency input frequency ?mhz thd ?dbc ?00 ?5 ?0 ?5 20 140 40 60 80 100 120 0 2v span 1v span ?0 ?5 tpc 8. thd vs. input frequency input frequency ?mhz snr ?dbc 77 67 69 20 140 40 60 80 100 120 0 +25 c +85 c ?0 c 71 73 75 tpc 9. snr vs. temperature and input frequency input frequency ?mhz snr ?dbc 20 140 40 60 80 100 120 0 75 65 67 69 71 73 2v span 1v span tpc 10. snr vs. input frequency input frequency ?mhz sfdr ?dbc 100 90 80 20 140 40 60 80 100 120 0 2v span 1v span 75 85 95 tpc 11. sfdr vs. input frequency input frequency ?mhz thd ?dbc 20 140 40 60 80 100 120 0 +25 c ?0 c ?2 ?8 ?4 ?2 ?6 ?0 ?0 ?6 ?4 ?8 +85 c tpc 12. thd vs. temperature and input frequency
rev. a ?2 ad9244 input frequency ?mhz harmonics ?dbc ?00 ?0 ?5 ?5 ?0 20 140 40 60 80 100 120 0 fourth harmonic second harmonic third harmonic ?5 tpc 13. harmonics vs. input frequency sample rate ?msps 75 70 20 40 60 80 100 0 sinad ?dbc f in = 20mhz f in = 10mhz f in = 2mhz 72 74 76 73 71 12.17 11.34 11.67 12.00 12.33 11.83 11.50 enob ?bits tpc 14. sinad vs. sample rate codes ?14-bit ?.5 inl ?lsb 1.5 1.0 0.5 ?.5 ?.0 0 16384 12288 8192 4096 0 tpc 15. typical inl duty cycle ?% 90 60 35 70 40 snr/sfdr ?dbc 45 50 55 60 65 85 80 75 70 65 snr, dcs on 30 95 100 sfdr, dcs on sfdr, dcs off snr, dcs off tpc 16. snr/sfdr vs. duty cycle, f in = 2.5 mhz sample rate ?msps sfdr ?dbc 100 88 84 80 20 40 60 80 100 0 92 96 f in = 2mhz f in = 10mhz f in = 20mhz tpc 17. sfdr vs. sample rate codes ?14-bit ?.0 dnl ?lsb 0.8 0.4 0.2 ?.2 ?.4 0 16384 12288 8192 4096 0 ?.6 ?.8 0.6 1.0 tpc 18. typical dnl
rev. a ad9244 ?3 0 ?20 amplitude ?dbfs ?0 ?0 ?0 ?0 ?00 snr = 67.5dbc sfdr = 79.4dbc frequency ?mhz 05 10 15 20 25 30 32.5 tpc 19. dual-tone fft with f in? = 44.2 mhz and f in? = 45.6 mhz (a in1 = a in2 = ?.5 dbfs) 0 ?20 amplitude ?dbfs ?0 ?0 ?0 ?0 ?00 frequency ?mhz 05 10 15 20 25 30 32.5 snr = 67.0dbc sfdr = 78.2dbc tpc 20. dual-tone fft with f in? = 69.2 mhz and f in? = 70.6 mhz (a in1 = a in2 = ?.5 dbfs) 0 ?20 amplitude ?dbfs ?0 ?0 ?0 ?0 ?00 snr = 65.0dbc sfdr = 69.1dbc frequency ?mhz 05 10 15 20 25 30 32.5 tpc 21. dual-tone fft with f in? = 139.2 mhz and f in? = 140.7 mhz (a in1 = a in2 = ?.5 dbfs) a in ?dbfs 40 ?5 dbfs and dbc ?0 ?5 ?0 ? 100 90 80 60 50 70 sfdr ?dbfs snr ?dbfs snr ?dbc sfdr ?dbc ?0 sfdr = 90dbc reference line tpc 22. dual-tone snr/sfdr vs. a in with f in? = 44.2 mhz and f in? = 45.6 mhz a in ?dbfs 40 ?5 dbfs and dbc ?0 ?5 ?0 ? 100 90 80 60 50 70 snr ?dbfs snr ?dbc sfdr ?dbc sfdr ?dbfs ?0 sfdr = 90dbc reference line tpc 23. dual-tone snr/sfdr vs. a in with f in? = 69.2 mhz and f in? = 70.6 mhz a in ?dbfs 40 ?5 dbfs and dbc ?0 ?5 ?0 ? 90 80 60 50 70 sfdr ?dbfs snr ?dbfs snr ?dbc sfdr ?dbc 100 ?0 sfdr = 90dbc reference line tpc 24. dual-tone snr/sfdr vs. a in with f in? = 139.2 mhz and f in? = 140.7 mhz typical if sampling performance
rev. a ?4 ad9244 0 ?20 amplitude ?dbfs ?0 ?0 ?0 ?0 ?00 snr = 62.6dbc sfdr = 60.7dbc frequency ?mhz 05 10 15 20 25 30 32.5 tpc 25. dual-tone fft with f in? = 239.1 mhz and f in? = 240.7 mhz (a in? = a in2 = ?.5 dbfs) 0 ?20 amplitude ?dbfs ?0 ?0 ?0 ?0 ?00 frequency ?mhz 05 10 15 20 25 30 32.5 snr = 73.0dbfs thd = ?9.5dbfs note: spur floor b elow 90dbfs @ 240mhz tpc 26. driving adc inputs with transformer and balun, f in = 240 mhz, a in = ?.5 dbfs input fr equency ?mhz 105 100 65 0 250 50 amplitude ?dbfs 100 150 200 85 80 75 70 95 90 tpc 27. cmrr vs. input frequency (a in = 0 dbfs and cml = 2.5 v) a in ?dbfs 40 ?5 dbfs and dbc ?0 ?5 ?0 ? 100 90 80 60 50 70 snr ?dbc ?0 sfdr ?dbfs snr ?dbfs sfdr ?dbc sfdr = 90dbc reference line t pc 28. dual-tone snr/sfdr vs. a in with f in? = 239.1 mhz and f in? = 240.7 mhz a in ?dbfs ?1 0 ?8 ?5 ?2 ? ? ? 95 55 dbfs and dbc 90 75 70 65 60 85 80 snr ?dbc snr ?dbfs sfdr ?dbc sfdr ?dbfs sfdr = 90dbc reference line tpc 29. driving adc inputs with transformer and balun snr/sfdr vs. a in , f in = 240 mhz a in ?dbfs ?1 0 ?8 ?5 ?2 ? ? ? 95 55 dbfs and dbc 90 75 70 65 60 85 80 snr ?dbc snr ?dbfs sfdr ?dbc sfdr ?dbfs sfdr = 90dbc reference line tpc 30. driving adc inputs with transformer and balun snr/sfdr vs. a in , f in = 190 mhz
rev. a ad9244 ?5 theory of operation the ad9244 is a high performance, single-supply 14-bit adc. in addition to high dynamic range nyquist sampling, it is designed for excellent if undersampling performance with an analog input as high as 240 mhz. the ad9244 uses a calibrated 10-stage pipeline architecture with a patented wideband, input sample-and-hold amplifier (sha) implemented on a cost-effective cmos process. each stage of the pipeline, excluding the last, consists of a low resolution flash adc along with a switched capacitor dac and interstage residue amplifier (mdac). the mdac amplifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. while the converter captures a new input sample every clock cycle, it takes eight clock cycles for the conversion to be fully processed and appear at the out- put as illustrated in figure 1. this latency is not a concern in many applications. the digital output, together with the otr indicator, is latched into an output buffer to drive the output pins. the output drivers of the ad9244 can be configured to interface with 5 v or 3.3 v logic families. the ad9244 has a duty clock stabilizer (dcs) that generates its own internal falling edge to create an internal 50% duty cycle clock, independent of the externally applied duty cycle. control of straight binary or twos complement output format is accom- plished with the dfs pin. the adc samples the analog input on the rising edge of the clock. while the clock is low, the input sha is in sample mode. when the clock transitions to a high logic level, the sha goes into the hold mode. system disturbances just prior to or imme- diately after the rising edge of the clock and/or excessive clock jitter may cause the sha to acquire the wrong input value and should be minimized. analog input and reference overview the differential input span of the ad9244 is equal to the potential at the vref pin. the vref potential may be obtained from the internal ad9244 reference or an external source. in differential applications, the center point of the input span is the common-mode level of the input signals. in single-ended applications, the center point is the dc potential applied to one input pin while the signal is applied to the opposite input pin. figures 3a to 3c show various system configurations. reft refb vref sense ad9244 vin+ vin 33 2.5v 1.5v 20pf 2v 10 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 33 2.5v 1.5v 50 refgnd + + figure 3a. 2 v p-p differential input, common-mode voltage = 2 v reft refb vref sense refgnd ad9244 vin+ vin 33 20pf 2v 10 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 33 3.0v 1.0v + + figure 3b. 2 v p-p single-ended input, common-mode voltage = 2 v 3.0v 2.0v 2.5v reft refb vref sense ad9244 vin+ vin 33 20pf 2v 10 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 33 3.0v 2.0v cml 2.5v 0.1 f 50 3.0v 2.0v refgnd + + figure 3c. 2 v p-p differential input, common-mode voltage = 2.5 v figure 4 is a simplified model of the ad9244 analog input, showing the relationship between the analog inputs, vin+, vin C , and the reference voltage, vref. note that this is only a sym- bolic model and that no actual negative voltages exist inside the ad9244. similar to the voltages applied to the top and bottom of the resistor ladder in a flash adc, the value vref/2 defines the minimum and maximum input voltages to the adc core. ad9244 14 adc core +vre f/2 ?ref/2 vin+ vin v core + figure 4. equivalent analog input of ad9244
rev. a ?6 ad9244 a differential input structure allows the user to easily configure the inputs for either single-ended or differential operation. the adc s input structure allows the dc offset of the input signal to be varied independent of the input span of the converter. specifi- cally, the input to the adc core can be de fined as the difference of the voltages applied at the vin+ and vin input pins. therefore, the equation v vin vin core =+ ?? (1) defines the output of the differential input stage and provides the input to the adc core. the voltage, v core , must satisfy the condition C // vref v vref core 22 << (2) where vref is the voltage at the vref pin. in addition to the limitations placed on the input voltages vin + and vin C by equations 1 and 2, boundaries on the inputs also exist based on the power supply voltages according to the conditions agnd v vin avdd v agnd v vin avdd v C .. C . C . 03 03 03 03 <+< + << + (3) where agnd is nominally 0 v and avdd is nominally 5 v. the range of valid inputs for vin+ and vin is any combination that satisfies both equations 2 and 3. for additional information showing the relationship between vin+, vin, vref, and the analog input range of the ad9244, see tables i and ii. analog input operation figure 5 shows the equivalent analog input of the ad9244, which consists of a 750 mhz differential sha. the differential input structure of the sha is flexible, allowing the device to be configured for either a differential or single-ended input. the analog inputs vin+ and vin C are interchangeable, with the exception that reversing the inputs to the vin+ and vin C pins results in a data inversion (complementing the output word). s s vin+ vin c pin, par s s h + c s c s c h c h c pin, par figure 5. analog input of ad9244 sha table i. analog input configuration summary input input input range (v) input cm connection coupling span (v) vin+ * vin C voltage comments single-ended dc or ac 1.0 0.5 to 1.5 1.0 1.0 best for stepped input response applications. 2.0 1 to 3 2.0 2.0 optimum noise performance for single-ended mode, often requires low distortion op amp with vcc > 5 v due to its headroom issues. differential dc or ac 1.0 2.25 to 2.75 2.75 to 2.25 2.5 optimum full-scale thd and sfdr performance well beyond the adc s nyquist frequency. 2.0 2.0 to 3.0 3.0 to 2.0 2.5 optimum noise performance for differential mode preferred mode for applications. * vin+ and vin C can be interchanged if data inversion is required. table ii. reference configuration summary reference input span (vin + C vin C ) operating mode connect to resulting vref (v) (v p-p) internal sense vref 1 1 internal sense agnd 2 2 internal r1 vref and sense 1 vref 2.0 1 span 2 r2 sense and refgnd vref = (1 + r1/r2) (span = vref) external sense avdd 1 vref 2.0 span = external ref vref external ref
rev. a ad9244 ?7 the optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 2 v input span) and matched input impedance for vin+ and vin C . only a slight degradation in dc linearity performance exists between the 2 v and 1 v input spans; however, the snr is lower in the 1 v input span. when the adc is driven by an op amp and a capacitive load is switched onto the output of the op amp, the output will momen- tarily drop due to its effective output impedance. as the output recovers, ringing may occur. to remedy the situation, a series resistor, r s , can be inserted between the op amp and the sha input as shown in figure 6. a shunt capacitance also acts like a charge reservoir, sinking or sourcing the additional charge required by the sampling capacitor, c s , further reducing current transients seen at the op amp s output. ad9244 vin+ vin vref sense refcom v cc v ee r s 33 r s 33 20pf 10 f 0.1 f + figure 6. resistors isolating sha input from op amp the optimum size of this resistor is dependent on several factors, including the adc sampling rate, the selected op amp, and the particular application. in most applications, a 30 ? to 100 ? resistor is sufficient. for noise sensitive applications, the very high bandwidth of the ad9244 may be detrimental and the addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the adc s input by forming a low-pass filter. the source imped ance driving vin+ and vin C should be matched. failure to provide matching may result in degradation of the snr, thd, and sfdr performance. differentially driving the analog inputs the ad9244 has a very flexible input structure, allowing it to interface with single-ended or differential inputs. the optimum mode of operation, analog input range, and associated interface circuitry will be determined by the particular application s performance requirements as well as power supply options. differential operation requires that vin+ and vin C be simulta- neously driven with two equal signals that are 180 out of phase with each other. differential modes of operation (ac-coupled or dc-coupled input) provide the best sfdr performance over a wide frequency range. they should be considered for the most demanding spectral-based applications (i.e., direct if conversion to digital). since not all applications have a signal precondition for differential operation, there is often a need to perform a single-ended-to- differential conversion. in systems that do not require dc coupling, an rf transformer with a center tap is the best method for generating differential input signals for the ad9244. this provides the benefit of operating the adc in the differential mode without contributing additional noise or distortion. an rf transformer also has the added benefit of providing electrical isolation between the signal source and the adc. the differential input characterization for this data sheet was performed using the configuration in figure 7. the circuit uses a mini-circuits ? rf transformer, model t1 C 1t, which has an impedance ratio of 1:1. this circuit assumes that the signal source has a 50 ? source impedance. the secondary center tap of the transformer allows a dc common-mode voltage to be added to the differential input signal. in figure 7, the center tap is con- nected to a resistor divider providing a half supply voltage. it could also be connected to the cml pin of the ad9244. it is recom- mended for if sampling applications (70 mhz < f in < 200 mhz) that the 20 pf differential capacitor between vin+ and vin C be reduced or removed. reft refb ad9244 vin+ vin 1k 0.1 f 0.1 f 0.1 f 10 f 1k 50 av d d 0.1 f r s 33 mini-circuits t1?t r s 33 20pf + figure 7. transformer-coupled input the circuit shown in figure 8 shows a method for applying a differential direct-coupled signal to the ad9244. an ad8138 amplifier is used to derive a differential signal from a single- ended signal. reft refb ad8138 ad9244 vin+ vin 1k 5v 0.1 f 0.1 f 0.1 f 10 f 499 50 1v p-p 0v av d d 10 f 0.1 f 10 f 0.1 f 0.1 f 499 499 475 1k 20pf 33 33 + + + figure 8. direct-coupled drive circuit with ad8138 differential op amp
rev. a ?8 ad9244 reference operation the ad9244 contains a band gap reference that provides a pin- strappable option to generate either a 1 v or 2 v output. with the addition of two external resistors, the user can generate reference voltages between 1 v and 2 v. another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance as described later in this section. figure 9a shows a simplified model of the internal voltage reference of the ad9244. a reference amplifier buffers a 1 v fixed reference. the output from the reference amplifier, a1, appears on the vref pin. as stated earlier, the voltage on the vref pin determines the full-scale differential input span of the adc. reft refb vref sense refgnd ad9244 to adc 2.5v a1 a2 1v logic disable a1 r r figure 9a. equivalent reference circuit the voltage appearing at the vref pin and the state of the internal reference amplifier, a1, are determined by the voltage present at the sense pin. the logic circuitry contains comparators that monitor the voltage at the sense pin. the various reference modes are summarized in table ii and are described in the next few sections. the actual reference voltages used by the internal circuitry of the ad9244 appear on the reft and refb pins. the voltages on these pins are symmetrical about midsupply or cml. for proper operation, it is necessary to add a capacitor network to decouple these pins. figure 9b shows the recommended decoupling network. the turn-on time of the reference voltage appearing between reft and refb is approximately 10 ms and should be taken into consideration in any power-down mode of operation. the vref pin should be bypassed to the refgnd pin with a 10 f tantalum capacitor in parallel with a low inductance 0.1 f ceramic capacitor. 10 f 0.1 f 0.1 f 0.1 f 0.1 f * 10 f vref reft refb ad9244 * locate as close as possible to reft/refb pins refgnd + + figure 9b. reference decoupling pin programmable reference by shorting the vref pin directly to the sense pin, the internal reference amplifier is placed in a unity gain mode and the resulting vref output is 1 v. by shorting the sense pin directly to the refgnd pin, the internal reference amplifier is configured for a gain of 2.0 and the resulting vref output is 2.0 v. resistor programmable reference figure 10 shows an example of how to generate a reference voltage other than 1.0 v or 2.0 v with the addition of two external resistors. use the equation vref v r r =+ () 1112 / to determine the appropriate values for r 1 and r 2. these resistors should be in the 2 k ? to 10 k ? range. for the example shown, r 1 equals 2.5 k ? and r 2 equals 5 k ? . from the equation above, the resulting reference voltage on the vref pin is 1.5 v. this sets the differential input span to 1.5 v p-p. the midscale voltage can also be set to vref by connecting vin ? to vref. 10 f 0.1 f 10 f 0.1 f 0.1 f 0.1 f reft refb vref sense refgnd ad9244 vin+ vin 3.25v 1.75v 2.5v 1.5v 33 33 20pf r1 2.5k r2 5k figure 10. resistor programmable reference (1.5 v p-p input span, differential input with vcm = 2.5 v) using an external reference to use an external reference, the internal reference must be disabled by connecting the sense pin to avdd. the ad9244 contains an internal reference buffer, a2 (see figure 9a), that simplifies the drive requirements of an external reference. the external reference must be able to drive a 5 k ? ( 20%) load. the bandwidth of the reference is deliberately left small to minimize the reference noise contribution. as a result, it is not possible to drive vref externally with high frequencies. figure 11 shows an example of an external reference driving both vin ? and vref. in this case, both the common-mode voltage and input span are directly dependent on the value of vref. both the input span and the center of the input span are equal to the external vref. thus the valid input range extends from (vref + vref/2) to (vref ? vref/2). for example, if the precision reference part, ref191, a 2.048 v external reference, is used, the input span is 2.048 v. in this case, 1 lsb of the ad9244 corresponds to 0.125 mv. it is essential that a minimum of a 10 f capacitor, in parallel with a 0.1 f low inductance ceramic capacitor, decouple the reference output to agnd. vin+ vref vin sense 20pf vref + vref/2 33 33 reft refb vref ?vref/2 vref 0.1 f 5v av d d 0.1 f 0.1 f 0.1 f 0.1 f 10 f + 10 f ad9244 figure 11. using an external reference
rev. a ad9244 ?9 digital inputs and outputs digital outputs table iii details the relationship among the adc input, otr, and digital output format. data format select (dfs) the ad9244 may be programmed for straight binary or twos complement data on the digital outputs. connect the dfs pin to agnd for straight binary and to avdd for twos complement. digital output driver considerations the ad9244 output drivers can be configured to interface with 5 v or 3.3 v logic families by setting drvdd to 5 v or 3.3 v, respectively. the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. how- ever, large drive currents tend to cause glitches on the supplies and may affect converter performance. applications requiring the adc to drive large capacitive loads or large fanouts may require external buffers or latches. out-of-range (otr) an out-of-range condition exists when the analog input voltage is beyond the input range of the adc. otr is a digital output that is updated along with the data output corresponding to the par- ticular sampled input voltage. thus, otr has the same pipeline latency as the digital data. otr is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range as shown in figure 12. otr will remain high until the analog input returns to within the input range and another conversion is completed. by logically and-ing otr with the msb and its complement, overrange high or underrange low conditions can be detected. table iv is a truth table for the overrange/underrange range circuit in figure 13, which uses nand gates. systems requiring programmable gain conditioning of the ad9244 can, after eight clock cycles, detect an out-of-range condition, thus eliminating gain selection iterations. also, otr can be used for digital offset and gain calibration. 1 1111 1111 1111 0 1111 1111 1111 0 1111 1111 1110 0 0000 0000 0001 0 0000 0000 0000 1 0000 0000 0000 otr data outputs otr +fs ?1 lsb +f s ?1/2 lsb +fs ?s ?s + 1/2 lsb ?s ?1/2 lsb figure 12. otr relation to input voltage and output data table iv. output data format otr msb analog input is 00w ithin range 01w ithin range 10u nderrange 11 overrange msb otr msb o ver = 1 under = 1 figure 13. overrange/underrange logic digital output enable function (oeb) the ad9244 has three-state ability. if the oeb pin is low, the output data drivers are enabled. if the oeb pin is high, the output data drivers are placed in a high impedance state. it is not intended for rapid access to the data bus. note that oeb is referenced to the digital supplies (drvdd) and should not exceed that supply voltage. table iii. output data format twos binary complement input (v) condition (v) output mode mode otr vin+ C vin C < C vref C 0.5 lsb 00 0000 0000 0000 10 0000 0000 0000 1 vin+ C vin C = C vref 00 0000 0000 0000 10 0000 0000 0000 0 vin+ C vin C = 0 10 0000 0000 0000 00 0000 0000 0000 0 vin+ C vin C = +vref C 1.0 lsb 11 1111 1111 1111 01 1111 1111 1111 0 vin+ C vin C > +vref C 0.5 lsb 11 1111 1111 1111 01 1111 1111 1111 1
rev. a ?0 ad9244 clock input considerations the analog input is sampled on the rising edge of the clock. timing variations, or jitter, on this edge causes the sampled input voltage to be in error by an amount proportional to the slew rate of the input signal and to the amount of the timing variation. thus, to maintain the excellent high frequency sfdr and snr characteristics of the ad9244, it is essential that the clock edge be kept as clean as possible. the clock should be treated like an analog signal. clock drivers should not share supplies with digital logic or noisy circuits. the clock traces should not run parallel to noisy traces. using a pair of symmetrically routed, differential clock signals can help to provide immunity from common-mode noise coupled from the environment. the clock receiver functions like a differential comparator. at the clk inputs, a slowly changing clock signal will result in more jitter than a rapidly changing one. driving the clock with a low amplitude sine wave input is not recommended. running a high speed clock through a divider circuit will provide a fast rise/fall time, resulting in the lowest jitter in most systems. clk+ clk ad9244 figure 15a. differential clock input?c-coupled clk+ clk ad9244 a gnd 0.1 f 1.6v figure 15b. single-ended clock input dc-coupled clk+ clk ad9244 a gnd figure 15c. single-ended input retains pin compatibility with ad9226 clock overview the ad9244 has a flexible clock interface that accepts either a single-ended or differential clock. an internal bias voltage facilitates ac coupling using two external capacitors. to remain backward compatible with the single-pin clock scheme of the ad9226, the ad9244 can be operated with a dc-coupled, single-pin clock by grounding the clk C pin and driving clk+. when the clk C pin is not grounded, the clk+ and clk C pins function as a differential clock receiver. when clk+ is greater than clk C , the sha is in hold mode; when clk+ is less than clk C , the sha is in track mode (see timing in figure 14). the rising edge of the clock (clk+ C clk C ) switches the sha from track to hold and timing jitter on this transition should be mini- mized, especially for high frequency analog inputs. it is often difficult to maintain a 50% duty cycle to the adc, especially when driving the clock with a single-ended or sine wave input. to ease the constraint of providing an accurate 50% clock, the adc has an optional internal duty cycle stabilizer (dcs) that allows the rising clock edge to pass through with minimal jitter and interpolates the falling edge, independent of the input clock falling edge. the dcs is described in greater detail in a later section. clock input modes figures 15a to 15e illustrate the modes of operation of the clock receiver. figure 15a shows a differential clock directly coupled to clk+ and clk C . in this mode, the common mode of the clk+ and clk C signals should be close to 1.6 v. figure 15b illustrates a single-ended clock input. the capacitor decouples the internal bias voltage on the clk C pin (about 1.6 v), establishing a threshold for the clk+ pin. figure 15c provides backward compatibility with the ad9226. in this mode, clk C is grounded and the threshold for clk+ is 1.5 v. figure 15d shows a differential clock ac-coupled by connecting through two capacitors. ac coupling a single-ended clock can also be accomplished using the circuit in figure 15e. when using the differential clock circuits of figure 15a or figure 15d, if clk C drops below 250 mv, the mode of the clock receiver may change, causing conversion errors. it is essential that clk C remain above 250 mv when the clock is ac-coupled or dc-coupled. clk clk+ clk clk+ sha in hold sha in track figure 14. sha timing
rev. a ad9244 ?1 speed. when the stabilizer is disabled, the internal switching will be directly affected by the clock state. if clk+ is high, the sha will be in hold mode; if clk+ is low, the sha will be in track mode. tpc 16 shows the benefits of using the clock stabilizer. connecting the dcs pin to avdd implements the internal clock stabilization function in the ad9244. if the dcs pin is connected to ground, the ad9244 will use both edges of the external clock in its internal timing circuitry (see specifications for timing requirements). grounding and decoupling analog and digital grounding proper grounding is essential in high speed, high resolution sys- tems. multilayer printed circuit boards (pcbs) are recommended to provide optimal grounding and power distribution. the use of power and ground planes offers distinct advantages, including: the minimization of the loop area encompassed by a signal and its return path. the minimization of the impedance associated with ground and power paths. the inherent distributed capacitor formed by the power plane, pcb material, and ground plane. it is important to design a layout that minimizes noise from coupling onto the input signal. digital input signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. while the ad9244 features separate analog and digital ground pins, it should be treated as an analog component. the agnd and dgnd pins must be joined together directly under the ad9244. a solid ground plane under the adc is acceptable if the power and ground return currents are carefully managed. analog supply decoupling the ad9244 features separate analog and digital supply and ground c ircuits, helping to minimize digital corruption of sensitive analog signals. in general, avdd (analog power) should be decoupled to agnd (analog ground). the avdd and agnd pi ns are adjacent to one another. figure 17 shows the recom- mended decoupling for each pair of analog supplies; 0.1 f ceramic chip and 10 f tantalum capacitors should provide adequately low impedance over a wide frequency range. the decoupling capacitors (especially 0.1 f) should be located as close to the pins as possible. ad9244 avdd agnd 10 f 0.1 f * * locate as close as possible to supply pins + figure 17. analog supply decoupling digital supply decoupling the digital activity on the ad9244 falls into two categories: correction logic and output drivers. the internal correction logic draws relatively small surges of current, mainly during the clock transitions. the output drivers draw large current impulses when the output bits change state. the size and duration of these currents are a function of the load on the output bits; large capacitive loads should be avoided. clk+ clk ad9244 100pf ?0.1 f figure 15d. differential clock input ac-coupled clk+ clk ad9244 a gnd 0.1 f 0.1 f 1.6 v figure 15e. single-ended clock input ac-coupled clock power dissipation most of the power dissipated by the ad9244 is from the analog power supplies. however, lower clock speeds will reduce digital supply current. figure 16 shows the relationship between power and clock rate. sample rate ?mhz 070 10 20 30 40 50 60 600 200 power ?mw 550 400 350 300 250 500 450 ad9244-40 ad9244-65 figure 16. power consumption vs. sample rate clock stabilizer (dcs) the clock stabilizer circuit in the ad9244 desensitizes the adc from clock duty cycle variations. system clock constraints are eased by internally restoring the clock duty cycle to 50%, inde- pendent of the clock input duty cycle. low jitter on the rising edge (sampling edge) of the clock is preserved while the falling edge is generated on-chip. it may be desirable to disable the clock stabilizer and may be necessary when the clock frequency is varied or completely stopped. note that stopping the clock is not recommended with ac-coupled clocks. once the clock frequency is changed, over 100 clock cycles may be required for the clock stabilizer to settle to the new
rev. a ?2 ad9244 from single-ended signals to differential. optimal ad9244 perfor- mance is achieved above 500 khz by using the input transformer. to drive the ad9244 via the transformer, connect solderable jumpers jp45 and jp46. dc bias is provided by the resistors r8 and r28. the evaluation board has positions for through-hole and surface- mount transformers. for applications requiring lower frequencies or dc applications, the ad8138 can be used. the ad8138 will provide good distortion and noise performance, as well as input buffering, up to 30 mhz. for more information, refer to the ad8138 data sheet. to use the ad8138 to drive the ad9244, remove the transformer (t1 or t4) and connect solderable jumpers jp42 and jp43. the ad9244 can be driven single-ended directly via s3 and can be ac-coupled or dc-coupled by removing or inserting jp5. to run the evaluation board in this way, remove the transformer (t1 or t4) and connect solderable jumpers jp40 and jp41. the resistors r40, r41, r8, and r28 are used to bias the ad9244 inputs to the correct common-mode levels in this application. reference configuration as described in the analog input and reference overview section earlier in this data sheet, the ad9244 can be configured to use its own internal or an external reference. an external reference, d3, and reference buffer, u5, are included on the ad9244 evaluation board. jumpers jp8 and jp22 C jp24 can be used to select the desired reference configuration (table vi). clock configuration the ad9244 evaluation board was designed to achieve optimal performance as well as to be easily configurable by the user. to configure the clock input, begin by connecting the correct com- bination of solderable jumpers jp11 C jp15 (table vii). the specific jumper configuration is dependent on the application and can be determined by referring to the clock input modes section. if the differential clock input mode is selected, an external sine wave generator applied to s5 can be used as the clock source. the clock buffer/drive mc10el16 from on semiconductor is used on the evaluation board to buffer and square the clock input. if the single-ended clock configuration is used, an external clock source can be applied to s1. the ad9244 evaluation board generates a buffered clock at ttl/cmos levels for use with a data capture system, such as the hsc-adc-eval-sc system. the clock buffering is provided by u4 and u7 and is configured by jumpers jp3, jp4, jp9, and jp18 (table vii). for the digital decoupling shown in figure 18, 0.1 f ceramic chip and 10 f tantalum capacitors are appropriate. the decou- pling capacitors (especially 0.1 f) should be located as close to the pins as possible. reasonable capacitive loads on the data pins are less than 20 pf per bit. applications involving greater digital loads should consider increasing the digital decoupling and/or using external buffers/latches. a complete decoupling scheme will also include large tantalum or electrolytic capacitors on the power supply connector to reduce low frequency ripple to insignificant levels. ad9244 drvdd dgnd 10 f 0.1 f * * locate as close as possible to supply pins + figure 18. digital supply decoupling cml the ad9244 has a midsupply reference point. this is used w ithin the internal architecture of the ad9244 and must be decoupled with a 0.1 f capacitor. it will source or sink a load of up to 300 a. if more current is required, the cml pin should be buffered with an amplifier. vr vr is an internal bias point on the ad9244. it must be decoupled to agnd with a 0.1 f capacitor. ad9244 cml 0.1 f 0.1 f vr figure 19. cml/vr decoupling evaluation board analog input configuration table v provides a summary of the analog input configuration. the analog inputs of the ad9244 on the evaluation board can be driven differentially through a transformer via connector s4, or the ad8138 amplifier via connector s2, or driven single-ended directly via connector s3. when using the transformer or ad8138 amplifier, a single-ended source may be used as both of these devices are configured on the ad9244 evaluation board to convert
rev. a ad9244 ?3 refin 10mhz refout signal synthesizer 2.5mhz, 0.8v p-p hp8644 clk synthesizer 65mhz, 1v p-p hp8644 2.5mhz band-pass filter avdd gnd dut avdd gnd dut dvdd dvdd ad9244 evaluation board output buss j1 s4 input xfmr s1/s5 input clock 5v + 5v ? 3v ? 3v ? dsp equipment clock divider figure 20. evaluation board connections table vi. reference jumper configuration reference voltage jumpers notes internal 2 v 23 jp8 not connected. internal 1 v 24 jp8 not connected. internal 1 v vref 2 v 25 jp8 not connected. vref = 1 + r1/r2. external 1 v vref 2 v 8, 22 set vref with r26. table vii. clock jumper configuration input connector jumpers dut clock differential s5 11, 13 single-ended s1 12, 15 data capture clock internal diff dut clock na 9, 18a se dut clock na 9, 18b external s6 3 or 4 table v. analog input jumper configuration input connector jumpers notes differential: transformer s4 45, 46 r8, r28 provide dc bias. optimal for 500 khz+. differential: amplifier s2 42, 43 remove t1 or t4. used for low input frequencies. single-ended s3 5, 40, 41 remove t1 or t4. jp5: connected for dc-coupled, not connected for ac-coupling.
rev. a ?4 ad9244 3 4 1 2 36 37 38 39 40 41 42 45 46 47 7 6 32 33 31 34 30 29 23 22 av d d av d d agnd agnd sense vref refgnd refb refb reft reft cml vin+ vin clk+ clk agnd agnd av d d av d d dgnd drvdd drvdd dgnd 28 27 26 25 24 21 20 19 18 17 16 13 12 11 10 8 9 48 35 43 5 44 15 14 otr msb-d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb-d0 nic oeb vr dfs dcs agnd nic drvdd dgnd otro u1 ad9226/ad9244 d13o d12o d11o d10o d9o d8o d7o d6o d5o d4o d3o d2o d1o d0o + c56 10 f 10v c57 0.1 f jp2 jp1 jp6 av d d c2 0.1 f r42 1k r6 1k r10 1k c40 0.001 f c45 0.001 f c1 10 f 10v dutdrvdd c37 0.1 f c38 0.1 f c23 10 f 10v dutavdd c42 0.001 f c41 0.001 f jp14 jp13 jp15 c30 0.1 f diffb jp12 seclk jp11 diffa c39 0.001 f c36 0.1 f c22 10 f 10v jp22 jp23 jp25 jp24 c35 0.1 f c21 10 f 10v r4 dnp r3 dnp wht dutavdd tp5 vin+ vin sheet3 sheet2 c50 0.1 f c33 0.1 f c20 0.1 f 10v c32 0.1 f c34 0.1 f 1 2 d3 r26 2k cw av d d r16 2.55k c29 0.1 f +in ?n out u5 ad822 1 3 2 a gnd; 4 av d d ; 8 r20 2k r17 2k jp8 c59 0.1 f c58 22 f 25v 2 tb1 3 tb1 a gnd fbead l1 tp2 red dutavdd dutavddin c53 0.1 f c48 22 f 25v 5 tb1 4 tb1 a gnd fbead l3 tp3 red dutdrvdd drvddin c52 0.1 f c47 22 f 25v 1 tb1 fbead l2 tp1 red av d d av ddin c14 0.1 f c6 22 f 25v 6 tb1 fbead l4 tp4 red dvdd dv ddin tp11 blk tp12 blk tp13 blk tp14 blk c28 0.1 f c27 10 f 10v av d d +in ?n out u5 ad822 7 5 6 a gnd; 4 av d d ; 8 figure 21. ad9244 evaluation board, adc, external reference, and power supply circuitry
rev. a ad9244 ?5 vcc q q vee reset clk clk vbb u3 mc10el16 1 2 3 4 8 7 6 5 r30 10k c60 0.01 f r38 10k r13 113 r15 90 av d d c19 0.1 f r23 33 c46 0.1 f diffa r25 33 c49 0.1 f diffb r12 113 r14 90 av d d c17 0.1 f av d d r43 100 r45 10k r44 100 cw av d d r39 49.9 c61 0.1 f diffclk s5 r11 49.9 18 116 rp1 22 y1 y2 y3 y4 y5 y6 y7 y8 17 215 rp1 22 16 314 rp1 22 15 413 rp1 22 14 512 rp1 22 13 611 rp1 22 12 710 rp1 22 11 89 rp1 22 a1 a2 y3 a4 a5 a6 a7 a8 2 3 4 5 6 7 8 9 u6 74vhc541 19 1 g2 g1 10 20 gnd vcc c12 0.1 f c4 10 f 10v + dvdd 18 116 rp2 22 y1 y2 y3 y4 y5 y6 y7 y8 17 215 rp2 22 16 314 rp2 22 15 413 rp2 22 14 512 rp2 22 13 611 rp2 22 12 710 rp2 22 11 89 rp2 22 a1 a2 y3 a4 a5 a6 a7 a8 2 3 4 5 6 7 8 9 u7 74vhc541 19 1 g2 g1 10 20 gnd vcc c11 0.1 f c5 10 f 10v + header right angle male no ejectors sam040ram j1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 msb clk otr d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 otr 18 rp3 22 otro otr 27 rp3 22 d13o d13 36 rp3 22 d12o d12 45 rp3 22 d11o d11 18 rp4 22 d10o d10 27 rp4 22 d9o d9 36 rp4 22 d8o d8 45 rp4 22 d7o d7 18 rp5 22 d6o d6 27 rp5 22 d5o d5 36 rp5 22 d4o d4 45 rp5 22 18 rp6 22 d3o d3 27 rp6 22 d2o d2 36 rp6 22 d1o d1 45 rp6 22 d0o d0 c10 0.1 f c3 10 f 10v av d d u4 decoupling u4 98 74vhc04 u4 11 10 74vhc04 r9 22 jp9 u4 34 74vhc04 u4 13 12 74vhc04 jp3 jp4 u4 56 74vhc04 av d d ; 14 a gnd; 7 r7 22 seclk u4 12 74vhc04 wht tp7 c13 0.1 f seclk s1 r1 49.9 jp18 a b 1 3 2 c31 0.1 f s6 data clk r29 49.9 r19 4k r2 5k r18 4k cw av d d av d d r27 2k cw c18 0.1 f c26 10 f 10v av d d u3 decoupling figure 22. ad9244 evaluation board, clock input, and digital output buffer circuitry
rev. a ?6 ad9244 c69 0.1 f c15 10 f 10v av d d s2 r31 49.9 ?n +in v v+ out out+ u2 ad8138 v ocm 1 8 6 5 3 4 2 r36 499 r35 499 amp input r34 523 r37 499 c8 0.1 f r32 10k r33 10k av d d r46 33 r47 33 jp42 jp40 jp45 r21 33 c44 dnp vin+ jp45 jp41 jp43 vin r22 33 c43 dnp c7 0.1 f r41 1k r40 1k av d d c9 0.33 f jp5 r5 49.9 single input s3 t4 nc= 2 ps adt4-6t t1 ps t1-1tx65 16 5 34 nc = 5 1 2 3 5 4 r24 49.9 s4 xfmrinput c24 20pf r8 500 c25 0.33 f c16 0.1 f av d d cw r28 2k sheet 1 figure 23. ad9244 evaluation board, analog input circuitry
rev. a ad9244 ?7 figure 24. ad9244 evaluation board, pcb assembly, top
rev. a ?8 ad9244 figure 25. ad9244 evaluation board, pcb assembly, bottom
rev. a ad9244 ?9 figure 26. ad9244 evaluation board, pcb layer 1 (top)
rev. a ?0 ad9244 figure 27. ad9244 evaluation board, pcb layer 2 (ground plane)
rev. a ad9244 ?1 figure 28. ad9244 evaluation board, pcb layer 3 (power plane)
rev. a ?2 ad9244 figure 29. ad9244 evaluation board, pcb layer 4 (bottom)
rev. a ad9244 ?3 outline dimensions 8-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc
rev. a ?4 ad9244 revision history location page 6/03?ata sheet changed from rev. 0 to rev. a changes to ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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